1. Field of the Invention
The present invention relates to an improvement of a digital chrominance signal processing circuit for a VTR for recording and reproducing chrominance signals included in video signals on the basis of low-band conversion thereof.
2. Description of the Prior Art
FIG. 1 shows an example of a prior art digital chrominance signal processing circuit, which has been disclosed in Proceedings of Television Institute, VOL. 15, No. 36, pp. 1 to 6. In FIG. 1, a dc-cutting circuit 100, a comb filter 108, a feed-forward APC (automatic phase control) circuit 114, and another comb filter 118 are used for reproducing video signals. On the other hand, an AFC (automatic frequency control) circuit 130 and a multiplier 132 are used for recording the video signals. Further, the remaining circuits other than those described above are used in common for recording and reproducing the video signals.
The chrominance signal reproducing operation will be first described hereinbelow. The dc components of the low-band converted chrominance signal data read from a video tape, for instance are cut off by the dc-cutting circuit 100, and then supplied to a multiplier 102. To this multiplier 102, a carrier signal is inputted from a carrier signal generator 112 controlled by a CPU 110. Therefore, an APC loop can be formed by these circuits 110 and 112 to execute a synchronous detection of the low-band converted carrier chrominance signal.
After that, the chrominance signal data are supplied to a decimation LPF 104 to eliminate unnecessary components and thin-out (extract) the data at a ratio of 1/6. The data outputted by the decimation LPF 104 are supplied to an ACC (automatic chroma level control) loop formed by a multiplier 106 and the CPU 110 to execute a burst ACC processing, so that the amplitude of the burst signal can be controlled to remain constant at all times.
Further, the processed data are supplied to the comb filter 108 to eliminate the crosstalk. The crosstalk, for example, arises in the chrominance signal between adjacent tracks of a video tape, the signal recorded thereon by the helical scanning system. The processed data are then supplied to the feed-forward APC circuit 114 to correct the residual phase error. The processed data are supplied to the comb filter 118 to improve the S/N ratio. Thereafter, the data are further processed through an additional function circuit 122 and an interpolation LPF 124, and then supplied to a multiplier 128 to multiply the data by a carrier signal outputted by a carrier generator 128, that is, to modulate the data to a carrier chrominance signal for reproduction of the chrominance signal.
The chrominance signal recording operation will be described hereinbelow. The high-band chrominance signal is inputted to a multiplier 102 via the dc-cutting circuit 100. This multiplier 102 executes the synchronous detection of the carrier chrominance signal through the APC loop formed by the CPU 110 and the carrier generator 112.
The data outputted by the multiplier 102 are supplied to the decimation LPF 104 to eliminate unnecessary components and thin-out (extract) the data at a ratio of 1/2. The data outputted by the decimation LPF 104 are supplied to the ACC loop formed by the multiplier 106 and the CPU 110 to execute a burst ACC processing and a chroma ACC processing, so that the peak level of chrominance signal can be controlled constant at all times. The processed data are supplied to the additional function circuit 122 via a switch 120 for CNR (chroma noise reduction) processing.
The data thus processed are supplied to the interpolation LPF 124 for data interpolation. The interpolated data are supplied to the multiplier 132. The multiplier 132 and the AFC circuit 130 are used to modulate the color difference signal to the low-band converted chrominance signal, and generate a carrier in synchronism with a horizontal synchronizing signal. As described above, it is possible to obtain the low-band converted chrominance signal data.
The above-mentioned prior art digital chrominance signal processing circuit is provided with the following features:
(1) The video signal can be processed after having been converted into the color difference signal.
(2) The ACC and APC can be processed in time serial manner under control of software management by the CPU.
(3) The feed-forward type APC can be adopted to improve the monochromatic S/N ratio against PM noise.
(4) After the processing by the multiplier 102 for synchronous detection, the clock frequency can be lowered to reduce the number of elements (such as delay circuits) during one horizontal scanning period (1H).
(5) The carrier generator 112 can be controlled by the CPU 110.
However, the prior art digital chrominance signal processing circuit involves the following drawbacks:
(1) Since the multipliers 102, 108, 128 and 132 are used, the number of gates (i.e., the number of elements) is large. In addition, since the PLL control is executed by integrating the phase difference information in the feedback APC with the use of the CPU 110 and the carrier generator 112, the number of data bits increases. Further, since a feed-forward APC circuit is incorporated in addition to the feedback APC control, and further since two control circuits are provided for both the APC circuits separately, the element construction is not effective. Further, since the two carrier generators 112 and 128 are provided for generating the sine wave signals used as frequency converting local carriers, some integrators and sine ROMs are required for each carrier generator respectively, thus increasing the circuit scale.
(2) In the case where hue varies, the circuit construction scale cannot be reduced (e.g., bit information cannot be reduced), because the S/N ratio deteriorates and consequently the resolution degrades.
(3) In comparison with the cost of the analog processing integrated circuits now on the market, the prior art circuit is very costly, so that it is impossible to adopt it for public use.